Welcome to Ulogic

Ulogic is a free software project aimed at netlist recovery from FPGA closed bitstream formats. It is the practical implementation of the work exposed in this paper.

The project features both command-line tools and graphical tools.

This wiki also contains information about how to reverse-engineer Altera chips.

  • AlteraReverse -- altera knowledge base for thoughts on how to approach altera reverse-engineering

This wiki also contains information about future projects and possible uses for debits:

  • CBits? -- JBits, only much, much, faster, in C, with bindings, with support for virtex4 and virtex5.

Project Status and latest news

The project can currently operate on the following Xilinx bitstream:

  • virtex2 bitstreams (from xc2v40 up to xc2v8000, NOT PRO),
  • virtex4 VLX bitstreams (xc4vlx25 through xc4vlx200),
  • virtex5 VLX bitstreams (xc5vlx30 through xc5vlx220, the 330 is not there because I could not generate any stream for it -- help me if you can !)
  • spartan3 bitstreams (from xc3s50 up to xc3s5000, NOT others A/AN/E). However, only CLB sites are supported for now.

All of these bitstreams are parsed, their pips can be dumped, nets can be rebuilt, and they *all* can be displayed -- see ScreenShots.

Virtex4, Virtex5 and Spartan3 are handled by separate binaries: debit_v4, debit_v5 and debit_s3 respectively for command-line operation, xiledit_v4, xiledit_v5 and xiledit_s3 respectively for graphical display. Save for Spartan3 support, these are now included in the windows installer.