Roadmap

• Milestone: spartan3

  No date set

• Milestone: virtex2

  No date set

  57%

  Closed tickets:

  4

  Active tickets:

  3

  Milestone targets:

  • Identify configuration bits for the slice
  • Identify parity bits of ramblocks
  • First target is generating a pseudo-xdl which will re-synthetize to the same bitstream for all bitstreams in the v2 family.

  • Higher-level netlist generation
  • Add support for long lines in the connexity analysis
  • Add support for LUT memory => eqn normal form
  • Add support for combining connexity analysis and normal form to yield full netlist

• Milestone: virtex4

  No date set

  0%

  Closed tickets:

  0

  Active tickets:

  1