Basic Altera toolchain usage

You must be familiar with the command-line Altera tools, in particular:

• the RCF (routing constraints file) format -- well documented in the QUIP, available from Altera's website here
• the back-annotation possibilities of the altera tools, which are heavily documented in the above documents

The first goal you should achieve is to make enough back-annotation so as to get deterministic place and route for a particular design. From this, everything will follow.

Also, i'm strongly advising you to get Altera's tools running under linux under wine, where you'll be able to perl and bash script their execution at leisure. A howto available. Or if you can afford it, have a native quartus linux version. I'm personally using the webpack QuartusII under wine.

Basics of the .sof file

The file is a standard binary format with the usual option type / option length / option payload format. It is well and clearly documented in the code itself, see for instance the bitstream_header.c file.

Basics of the bitstream geometry

Once you have a deterministic PAR, it's relatively easy to change some bits in the LUT tables so as to locate the LUT table bits themselves. This will give you a very rough overview of the overall bitstream geometry.

Advanced bitstream geometry

Contrary to Xilinx's chips, which are a breeze to reverse due to their highly regular nature, Altera's chips are much less regular. In a first approximation, to be confirmed, one can assume that:

• the low-level fundamentals (how many muxes, how they are controlled) are regular
• the copper wiring between the above primitives can change from one block to the next

This leads to a two-stage reverse (when Xilinx only needs the first stage):

• Isolate the low-level configuration bit patterns in the bitstream (O(1) in chip size over a chip family)
• For each site, infer what the connexion (O(chip size), to be repeated for every chip in the family)