Data example meaning

Validation

xdl2ncd then netgen

=> get back VHDL from the xdl. So what's left to do is just the bit2xdl tool. Yeah !

Demo

The above data presents simple examples that you can download and try debit with without necessarily having specific bitstream at hand. This is of paramount importance as

  • there is a very wide variety of xilinx chips;
  • I don't have the ressources to reverse them all for now;
  • you may not have the time to generate specific bitfiles

Testing

This data provides input test data for the test suite.

Testsets

Debit testsets should include:

  • ncd files
  • uncompressed and compressed bitfiles
  • reference output from debit and associated debit command-line

Although everything else could be rebuild from ncd, this allows easy demo and non-regression testing.

The directory layout should be as thus:

  • everything in a $chipfamily/ directory
  • with $chip subdirectory/
  • with $design subdirectory, containing $design.ncd, $design.bit, $design_u.bit and $design#.ref and $design#.cmd

The actual test sequence will:

  • run debit dumpframe on the uncompressed and compressed bitstream, and compare both
  • may run bitgen if found in path, in debug mode, to check the frames against
  • run debit for as many .cmd references as found, and compare the debit (std)output to the associated .ref file

Simple designs

The test suite has very simple designs that can be hand-verified if need be. These very small testcases should span on the whole range of chips in a family, and they are used to check very straightforward properties such as:

  • are compressed / uncompressed bitstreams handled properly ?
  • is debitting rightly done for all chips in a family ?

Complex designs

Complex designs are aimed at getting to the corner cases of a bitstream. This is where opencores should be tried. Typically, only one bitstream for a whole family should be sufficient. These are used to make sure that all the data is duly extracted from the bitstream.

TODO

I'd like to get .ncds from opencores GPL designs as both simple and complex examples, instead of the xilinx-provided examples, which may put me at odds with their legal department. As far as complex designs are concerned, I don't have examples at hand which I can distribute freely.

Virtex2 family examples

These bitstreams and NCDs are distributed separately to as to be able to pull them out in case of legal emergency.

Steps to take to be able to use them:

  • Download them
  • Unpack them
  • If you have the code, and want to run extensive checks, untar in the tests/ subdirectory of the source tree

Simple designs

For each virtex2 chip, this tarball contains

  • the jc2_top example from Xilinx

Complex designs

I'm only providing the bitfile there, pending a good opencores design. This is an xc2v2000 bitstream which contains proprietary data.

Virtex4 family examples

Simple designs